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» The behavior of resistive circuits
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EURODAC
1994
IEEE
130views VHDL» more  EURODAC 1994»
13 years 11 months ago
RESIST: a recursive test pattern generation algorithm for path delay faults
This paper presents Resist, a recursive test pattern generation (TPG) algorithm for path delay fault testing of scan-based circuits. In contrast to other approaches, it exploits t...
Karl Fuchs, Michael Pabst, Torsten Rössel
ASPDAC
2005
ACM
107views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Substrate resistance extraction with direct boundary element method
- It is important to model the substrate coupling for mixed-signal circuit designs today. This paper presents the direct boundary element method (BEM) for substrate resistance calc...
Xiren Wang, Wenjian Yu, Zeyi Wang
TC
1998
13 years 7 months ago
Multiple-Valued Signed-Digit Adder Using Negative Differential-Resistance Devices
—This paper describes a new signed-digit full adder (SDFA) circuit consisting of resonant-tunneling diodes (RTDs) and metal-oxide semiconductor field effect transistors (MOSFETs)...
Alejandro F. González, Pinaki Mazumder
CORR
2007
Springer
106views Education» more  CORR 2007»
13 years 7 months ago
Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design
: New nanotechnology based devices are replacing CMOS devices to overcome CMOS technology’s scaling limitations. However, many such devices exhibit nonmonotonic I-V characteristi...
Bharat Sukhwani, Uday Padmanabhan, Janet Meiling W...
VTS
2007
IEEE
105views Hardware» more  VTS 2007»
14 years 1 months ago
Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance
Attack resistance has been a critical concern for security-related applications. Various side-channel attacks can be launched to retrieve security information such as encryption k...
Chunsheng Liu, Yu Huang