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ICCD
2004
IEEE
112views Hardware» more  ICCD 2004»
14 years 4 months ago
An Infrastructure IP for On-Chip Clock Jitter Measurement
In this paper, we present an infrastructure IP core to facilitate on-chip clock jitter measurement. In the proposed approach, the clock signal under test is delayed by two differe...
Jui-Jer Huang, Jiun-Lang Huang
ICCAD
2003
IEEE
124views Hardware» more  ICCAD 2003»
14 years 4 months ago
A Statistical Approach to Estimate the Dynamic Non-Linearity Parameters of Pipeline ADCs
A fully-analytical approach to estimate the statistics of dynamic non-linearity parameters of pipeline analog-todigital converters (ADCs) in the presence of circuit nonidealities ...
Mohammad Taherzadeh-Sani, Reza Lotfi, Omid Shoaei
DATE
2008
IEEE
121views Hardware» more  DATE 2008»
14 years 2 months ago
Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures
As levels of parallelism are becoming increasingly complex in multiprocessor architectures, GALS, and asynchronous circuits, methodologies and software tools are needed to verify ...
Nicolas Coste, Hubert Garavel, Holger Hermanns, Ri...
FPL
2001
Springer
102views Hardware» more  FPL 2001»
14 years 6 days ago
A Generic Library for Adaptive Computing Environments
The Generic Library for Adaptive Computing Environments (GLACE) consists of a comprehensive set of module generators currently targeting Xilinx XC4000 and Virtex devices. In contra...
Tilman Neumann, Andreas Koch
RSP
1998
IEEE
109views Control Systems» more  RSP 1998»
13 years 11 months ago
A Technique for Combined Virtual Prototyping and Hardware Design
A technique to include virtual prototyping in the design cycle of complex digital modem ASICs is presented. It is innovating by using the same behavioral description for both the ...
Patrick Schaumont, Geert Vanmeerbeeck, E. Watzeels...