In this paper, we present an infrastructure IP core to facilitate on-chip clock jitter measurement. In the proposed approach, the clock signal under test is delayed by two differe...
A fully-analytical approach to estimate the statistics of dynamic non-linearity parameters of pipeline analog-todigital converters (ADCs) in the presence of circuit nonidealities ...
As levels of parallelism are becoming increasingly complex in multiprocessor architectures, GALS, and asynchronous circuits, methodologies and software tools are needed to verify ...
Nicolas Coste, Hubert Garavel, Holger Hermanns, Ri...
The Generic Library for Adaptive Computing Environments (GLACE) consists of a comprehensive set of module generators currently targeting Xilinx XC4000 and Virtex devices. In contra...
A technique to include virtual prototyping in the design cycle of complex digital modem ASICs is presented. It is innovating by using the same behavioral description for both the ...
Patrick Schaumont, Geert Vanmeerbeeck, E. Watzeels...