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ACSD
1998
IEEE
90views Hardware» more  ACSD 1998»
14 years 27 days ago
Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation
This paper makes the idea of memory shadowing [5] applicable to symbolic ternary simulation. Memory shadowing, an extension of Burch and Dill's pipeline verification method [...
Miroslav N. Velev, Randal E. Bryant
GLVLSI
1997
IEEE
105views VLSI» more  GLVLSI 1997»
14 years 25 days ago
OLIVIA: Objectoriented Logicsimulation Implementing the VITAL Standard
In a VHDL-based design flow for applicationspecific integrated circuits, VITAL provides a uniform methodology for developing ASIC libraries for signoff simulation. The VITAL Sta...
Josef Fleischmann, Rolf Schlagenhaft, Martin Pelle...
DAC
1997
ACM
14 years 25 days ago
Sequence Compaction for Probabilistic Analysis of Finite-State Machines
- The objective of this paper is to provide an effective technique for accurate modeling of the external input sequences that affect the behavior of Finite State Machines (FSMs). T...
Diana Marculescu, Radu Marculescu, Massoud Pedram
DAC
1997
ACM
14 years 25 days ago
Hierarchical Sequence Compaction for Power Estimation
- This paper presents an effective technique for compacting a large sequence of input vectors into a much smaller one such that when the two sequences are applied to any circuit, t...
Radu Marculescu, Diana Marculescu, Massoud Pedram
INFOCOM
1993
IEEE
14 years 23 days ago
An Analysis of the Congestion Effects of Link Failures in Wide Area Networks
Here we present the results of a study to determine the effects of link failures on network performance. The network studied is a virtual circuit based packet switched wide area n...
David Tipper, Joseph L. Hammond, S. Sharma, A. Khe...