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CORR
2006
Springer
112views Education» more  CORR 2006»
13 years 8 months ago
High-level synthesis under I/O Timing and Memory constraints
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...
Philippe Coussy, Gwenolé Corre, Pierre Bome...
IJON
2006
73views more  IJON 2006»
13 years 8 months ago
Selective attention implemented with dynamic synapses and integrate-and-fire neurons
Selective attention is a process widely used by biological sensory systems to overcome the problem of limited parallel processing capacity: salient subregions of the input stimuli...
Chiara Bartolozzi, Giacomo Indiveri
NN
1998
Springer
13 years 8 months ago
Neural control of rhythmic arm movements
In this paper we present an approach to robot arm control based on exploiting the dynamical properties of a simple neural network oscillator circuit coupled to the joints of an ar...
Matthew M. Williamson
FPL
2010
Springer
106views Hardware» more  FPL 2010»
13 years 6 months ago
Increasing Design Productivity through Core Reuse, Meta-data Encapsulation, and Synthesis
This paper presents a novel IP core reuse strategy which reduces design time from days to hours for communication circuits such as digital radio receivers. This design productivity...
Adam Arnesen, Kevin Ellsworth, Derrick Gibelyou, T...
UC
2010
Springer
13 years 6 months ago
Majority Adder Implementation by Competing Patterns in Life-Like Rule B2/S2345
We study Life-like cellular automaton rule B2/S2345. This automaton exhibits a chaotic behavior yet capable for purposeful computation. The automaton implements Boolean gates via p...
Genaro Juárez Martínez, Kenichi Mori...