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ISCA
2006
IEEE
142views Hardware» more  ISCA 2006»
14 years 1 months ago
Bulk Disambiguation of Speculative Threads in Multiprocessors
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
Luis Ceze, James Tuck, Josep Torrellas, Calin Casc...
IPPS
2010
IEEE
13 years 5 months ago
A lock-free, cache-efficient multi-core synchronization mechanism for line-rate network traffic monitoring
Line-rate data traffic monitoring in high-speed networks is essential for network management. To satisfy the line-rate requirement, one can leverage multi-core architectures to par...
Patrick P. C. Lee, Tian Bu, Girish P. Chandranmeno...
PSTV
1993
123views Hardware» more  PSTV 1993»
13 years 8 months ago
On the Verification of Temporal Properties
We present a new algorithm that can be used for solving the model−checking problem for linear−time temporal logic. This algorithm can be viewed as the combination of two exist...
Patrice Godefroid, Gerard J. Holzmann
CIKM
2008
Springer
13 years 9 months ago
Cache-aware load balancing for question answering
The need for high performance and throughput Question Answering (QA) systems demands for their migration to distributed environments. However, even in such cases it is necessary t...
David Dominguez-Sal, Mihai Surdeanu, Josep Aguilar...
LATIN
2010
Springer
14 years 1 months ago
The I/O Complexity of Sparse Matrix Dense Matrix Multiplication
We consider the multiplication of a sparse N × N matrix A with a dense N × N matrix B in the I/O model. We determine the worst-case non-uniform complexity of this task up to a c...
Gero Greiner, Riko Jacob