56 search results - page 6 / 12 » The chained-cubic tree interconnection network |
DSD
2007
IEEE
14 years 1 months ago
2007
IEEE
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
ALGORITHMICA
2006
13 years 7 months ago
2006
We present some fundamental structural properties for minimum length networks (known as Steiner minimum trees) interconnecting a given set of points in an environment in which edg...
INFOCOM
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract— The goal of data center networking is to interconnect a large number of server machines with low equipment cost, high and balanced network capacity, and robustness to l...
ISPD
2006
ACM
14 years 1 months ago
2006
ACM
Advances in VLSI technology make clock skew more susceptible to process variations. Notwithstanding efficient zero skew routing algorithms, clock skew still limits post-manufactu...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
Post-silicon validation has become an essential step in the design flow of today's complex integrated circuits. One effective technique that provides real-time visibility to ...