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DAC
2005
ACM
14 years 9 months ago
Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration
Many reconfigurable architectures offer partial dynamic configurability, but current system-level tools cannot guarantee feasible implementations when exploiting this feature. We ...
Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. D...
DAC
2010
ACM
14 years 22 days ago
Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms
We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...
Chenjie Yu, Peter Petrov
FCCM
2009
IEEE
134views VLSI» more  FCCM 2009»
14 years 21 days ago
Efficient Mapping of Hardware Tasks on Reconfigurable Computers Using Libraries of Architecture Variants
Scheduling and partitioning of task graphs on reconfigurable hardware needs to be carefully carried out in order to achieve the best possible performance. In this paper, we demons...
Miaoqing Huang, Vikram K. Narayana, Tarek A. El-Gh...
DSD
2008
IEEE
104views Hardware» more  DSD 2008»
13 years 9 months ago
A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures
Efficient utilization of multi-core architectures relies on the partitioning of applications into tasks and mapping the tasks to cores. In some applications (e.g. H.264 video deco...
Magnus Själander, Andrei Terechko, Marc Duran...
NIPS
2008
13 years 10 months ago
Clustered Multi-Task Learning: A Convex Formulation
In multi-task learning several related tasks are considered simultaneously, with the hope that by an appropriate sharing of information across tasks, each task may benefit from th...
Laurent Jacob, Francis Bach, Jean-Philippe Vert