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ECRTS
2009
IEEE
13 years 7 months ago
On the Design and Implementation of a Cache-Aware Multicore Real-Time Scheduler
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
John M. Calandrino, James H. Anderson
EUROPAR
2003
Springer
14 years 3 months ago
Implementation of a Grid Computation Toolkit for Design Optimisation with Matlab and Condor
The process of design search and optimisation is characterised by its computationally intensive operations, which produce a problem well suited to Grid computing. Here we present a...
Gang Xue, Matt J. Fairman, Graeme E. Pound, Simon ...
SAINT
2008
IEEE
14 years 4 months ago
Design and Implementation of Sensor Network on the NGN/IMS
The sensor networks had been used for various application areas and showed effectiveness under the prior application planning and right circumstances that includes cost, data hand...
Yasuhiro Araki, Minh Tuan Nguyen, Hiroyuki Morikaw...
FPGA
2007
ACM
114views FPGA» more  FPGA 2007»
14 years 4 months ago
Design of a logic element for implementing an asynchronous FPGA
A reconfigurable logic element (LE) is developed for use in constructing a NULL Convention Logic (NCL) FPGA. It can be configured as any of the 27 fundamental NCL gates, including...
Scott C. Smith
MSS
2003
IEEE
113views Hardware» more  MSS 2003»
14 years 3 months ago
Design and Implementation of Multiple Addresses Parallel Transmission Architecture for Storage Area Network
In this paper, we present a parallel transmission architecture for SAN. By using two schedulers on the destination and source addresses of packets, the load of multiple data flows...
Bin Meng, Patrick B. T. Khoo, T. C. Chong