Design of a logic element for implementing an asynchronous FPGA

A reconfigurable logic element (LE) is developed for use in constructing a NULL Convention Logic (NCL) FPGA. It can be configured as any of the 27 fundamental NCL gates, including resettable and inverting variations, and can utilize embedded registration for gates with three or fewer inputs. The developed LE is compared with a previous NCL LE, showing that the one developed herein yields a more area efficient NCL circuit implementation. The NCL FPGA logic element is simulated at the

• Type: Conference
• Year: 2007
• Where: FPGA
• Authors: Scott C. Smith
• Keywords: Area Efficient Ncl, FPGA 2007, Fundamental Ncl Gates, Hardware, NCL FPGA Logic