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» The design of a high performance low power microprocessor
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ICCD
2007
IEEE
182views Hardware» more  ICCD 2007»
14 years 3 months ago
Reducing leakage power in peripheral circuits of L2 caches
Leakage power has grown significantly and is a major challenge in microprocessor design. Leakage is the dominant power component in second-level (L2) caches. This paper presents t...
Houman Homayoun, Alexander V. Veidenbaum
USENIX
2003
13 years 10 months ago
Design and Implementation of Power-Aware Virtual Memory
Despite constant improvements in fabrication technology, hardware components are consuming more power than ever. With the everincreasing demand for higher performance in highly-in...
Hai Huang, Padmanabhan Pillai, Kang G. Shin
DATE
2002
IEEE
84views Hardware» more  DATE 2002»
14 years 1 months ago
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications
Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of ...
Gilles Sassatelli, Lionel Torres, Pascal Benoit, T...
CORR
2008
Springer
96views Education» more  CORR 2008»
13 years 9 months ago
High Efficiency 3-Phase Cmos Rectifier with Step Up and Regulated
: This paper presents several design issues related to the monolithic integration of a 3-phase AC to DC low voltage, low power rectifier for 3-phase micro source electrical conditi...
J.-C. Crebier, Y. Lembeye, H. Raisigel, O. Deleage...
KES
2005
Springer
14 years 2 months ago
Reconfigurable Power-Aware Scalable Booth Multiplier
Abstract. An energy-efficient power-aware design is highly desirable for digital signal processing functions that encounter a wide diversity of operating scenarios in battery-power...
Hanho Lee