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» The design of a high performance low power microprocessor
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HPCA
1996
IEEE
14 years 1 months ago
Co-Scheduling Hardware and Software Pipelines
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...
ASYNC
2007
IEEE
154views Hardware» more  ASYNC 2007»
14 years 3 months ago
Design of a High-Speed Asynchronous Turbo Decoder
This paper explores the advantages of high performance asynchronous circuits in a semi-custom standard cell environment for high-throughput turbo coding. Turbo codes are high-perf...
Pankaj Golani, Georgios D. Dimou, Mallika Prakash,...
MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
13 years 8 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...
INFOCOM
2012
IEEE
11 years 11 months ago
LBA: Lifetime balanced data aggregation in low duty cycle sensor networks
—This paper proposes LBA, a lifetime balanced data aggregation scheme for asynchronous and duty cycle sensor networks under an application-specific requirement of end-to-end dat...
Zi Li, Yang Peng, Daji Qiao, Wensheng Zhang
CF
2006
ACM
14 years 21 days ago
The potential of the cell processor for scientific computing
The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As...
Samuel Williams, John Shalf, Leonid Oliker, Shoaib...