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» The design of a high performance low power microprocessor
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ASPDAC
2007
ACM
88views Hardware» more  ASPDAC 2007»
14 years 26 days ago
Voltage Island Generation under Performance Requirement for SoC Designs
Using multiple supply voltages on a SoC design is an efficient way to achieve low power. However, it may lead to a complex power network and a huge number of level shifters if we j...
Wai-Kei Mak, Jr-Wei Chen
CASES
2006
ACM
14 years 2 months ago
FlashCache: a NAND flash memory file cache for low power web servers
We propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms. Our architecture uses a two level file buffer cache composed of a re...
Taeho Kgil, Trevor N. Mudge
VLSID
2002
IEEE
149views VLSI» more  VLSID 2002»
14 years 9 months ago
Functional Partitioning for Low Power Distributed Systems of Systems-on-a-Chip
In this paper, we present a functional partitioning method for low power real-time distributed embedded systems whose constituent nodes are systems-on-a-chip (SOCs). The systemlev...
Yunsi Fei, Niraj K. Jha
AUTOID
2005
IEEE
14 years 2 months ago
An Ultra-Low Power, Optically-Interrogated Smart Tagging and Identification System
We present a wireless identification system that employs an optical communications link between an array of uniquely identifiable smart tags and an interrogator flashlight. As the...
Gerardo Barroeta Perez, Mateusz Malinowski, Joseph...
JCP
2008
160views more  JCP 2008»
13 years 8 months ago
A Bluetooth-based Sensor Node for Low-Power Ad Hoc Networks
TCP/IP has recently taken promising steps toward being a viable communication architecture for networked sensor nodes. Furthermore, the use of Bluetooth can enable a wide range of ...
Jens Eliasson, Per Lindgren, Jerker Delsing