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» The design of a high performance low power microprocessor
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ICCD
2003
IEEE
121views Hardware» more  ICCD 2003»
14 years 5 months ago
Distributed Reorder Buffer Schemes for Low Power
We consider several approaches for reducing the complexity and power dissipation in processors that use separate register file to maintain the commited register values. The first ...
Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad ...
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
14 years 2 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
ASPLOS
2004
ACM
14 years 2 months ago
Fingerprinting: bounding soft-error detection latency and bandwidth
Recent studies have suggested that the soft-error rate in microprocessor logic will become a reliability concern by 2010. This paper proposes an efficient error detection techniqu...
Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Baba...
LREC
2010
196views Education» more  LREC 2010»
13 years 10 months ago
Event Models for Historical Perspectives: Determining Relations between High and Low Level Events in Text, Based on the Classifi
In this paper, we report on a study that was performed within the "Semantics of History" project on how descriptions of historical events are realized in different types...
Agata Cybulska, Piek Vossen
TMC
2010
112views more  TMC 2010»
13 years 7 months ago
Comparison of Data-Driven Link Estimation Methods in Low-Power Wireless Networks
Abstract—Link estimation is a basic element of routing in lowpower wireless networks, and data-driven link estimation using unicast MAC feedback has been shown to outperform broa...
Hongwei Zhang, Lifeng Sang, Anish Arora