517 search results - page 19 / 104 » The design of a low energy FPGA |
CF
2005
ACM
13 years 10 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
IPPS
2008
IEEE
14 years 2 months ago
2008
IEEE
Packet classification is an important function in a router’s line-card. Although many excellent solutions have been proposed in the past, implementing high speed packet classifi...
PATMOS
2000
Springer
14 years 7 hour ago
2000
Springer
Abstract. The emergence of data-intensive applications in mobile environments has resulted in portable electronic systems with increasingly large dynamic memories. The typical oper...
DAC
1995
ACM
13 years 12 months ago
1995
ACM
We propose a novel optimization scheme that can improve the routing by reducing a newly observed router decaying effect. A pair of greedy-grow algorithms, each emphasizing a diffe...
ANCS
2008
ACM
13 years 10 months ago
2008
ACM
Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Inte...