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» The design of a low energy FPGA
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CHES
2005
Springer
123views Cryptology» more  CHES 2005»
14 years 2 months ago
Improved Higher-Order Side-Channel Attacks with FPGA Experiments
We demonstrate that masking a block cipher implementation does not sufficiently improve its security against side-channel attacks. Under exactly the same hypotheses as in a Differ...
Eric Peeters, François-Xavier Standaert, Ni...
DFT
1999
IEEE
125views VLSI» more  DFT 1999»
14 years 23 days ago
Algorithms for Efficient Runtime Fault Recovery on Diverse FPGA Architectures
The inherent redundancy and in-the-field reconfiguration capabilities of field programmable gate arrays (FPGAs) provide alternatives to integrated circuit redundancy-based fault r...
John Lach, William H. Mangione-Smith, Miodrag Potk...
RECONFIG
2008
IEEE
268views VLSI» more  RECONFIG 2008»
14 years 2 months ago
Parametric, Secure and Compact Implementation of RSA on FPGA
1 We present a fast, efficient, and parameterized modular multiplier and a secure exponentiation circuit especially intended for FPGAs on the low end of the price range. The desig...
Ersin Oksuzoglu, Erkay Savas
AHS
2007
IEEE
349views Hardware» more  AHS 2007»
14 years 2 months ago
A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm
In this paper, we present a low power implementation of H.264 adaptive deblocking filter (DBF) algorithm on ARM Versatile / PB926EJ-S Development Board. The DBF hardware is implem...
Mustafa Parlak, Ilker Hamzaoglu
CASES
2004
ACM
14 years 1 months ago
A low power architecture for embedded perception
Recognizing speech, gestures, and visual features are important interface capabilities for future embedded mobile systems. Unfortunately, the real-time performance requirements of...
Binu K. Mathew, Al Davis, Michael Parker