517 search results - page 42 / 104 » The design of a low energy FPGA |
FPL
2007
Springer
14 years 2 months ago
2007
Springer
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of powe...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
High reliability against noise, low energy consumption and high performance are key objectives in the design of on-chip networks. Recently some researchers have considered the var...
INFOCOM
2009
IEEE
14 years 3 months ago
2009
IEEE
—Network protocols have traditionally been designed using a layered method in part because it is easier to implement some portions of network protocols in software and other port...
AVSS
2009
IEEE
13 years 6 months ago
2009
IEEE
Low-cost and low-power video surveillance systems based on networks of wireless video sensors will enter soon the marketplace with the promise of flexibility, quick deployment an...
SQJ
2002
13 years 8 months ago
2002
Acknowledging the intense requirement for low power operation in most portable computing systems, this paper introduces the notion of energy efficient software design and proposes ...