517 search results - page 45 / 104 » The design of a low energy FPGA |
ASPDAC
2007
ACM
14 years 15 days ago
2007
ACM
The development cost of low-power embedded systems can be significantly reduced by reusing legacy designs and applying proper modifications to meet the new power constraints. The ...
VLSISP
2010
13 years 6 months ago
2010
A Split decoding algorithm is proposed which divides each row of the parity check matrix into two or multiple nearly-independent simplified partitions. The proposed method signific...
CODES
2007
IEEE
14 years 13 days ago
2007
IEEE
Energy consumption is a major issue in dynamically reconfigurable systems because of the high power requirements during repeated configurations. Hardware designs employ low power ...
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
LCTRTS
2007
Springer
14 years 2 months ago
2007
Springer
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...