517 search results - page 65 / 104 » The design of a low energy FPGA |
ISLPED
2009
ACM
14 years 1 months ago
2009
ACM
An energy efficient object recognition processor is proposed for real-time visual applications. Its energy efficiency is improved by lowering average power consumption while susta...
FCCM
2011
IEEE
12 years 11 months ago
2011
IEEE
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...
FCCM
2006
IEEE
14 years 1 months ago
2006
IEEE
Current Radio Frequency Identification (RFID) systems generally have long design times and low tolerance to changes in specification. This paper describes a field programmable,...
CDES
2006
13 years 8 months ago
2006
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
ERSA
2008
13 years 8 months ago
2008
For two decades, reconfigurable computing systems have provided an attractive alternative to fixed hardware solutions. Reconfigurable computing systems have demonstrated the low c...