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CF
2010
ACM
14 years 12 days ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
CODES
2008
IEEE
14 years 1 months ago
Static analysis of processor stall cycle aggregation
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
Jongeun Lee, Aviral Shrivastava
CORR
2007
Springer
114views Education» more  CORR 2007»
13 years 7 months ago
High Performance Direct Gravitational N-body Simulations on Graphics Processing Units
We present the results of gravitational direct N-body simulations using the commercial graphics processing units (GPU) NVIDIA Quadro FX1400 and GeForce 8800GTX, and compare the re...
Simon Portegies Zwart, Robert G. Belleman, Peter G...
DAC
2004
ACM
14 years 8 months ago
Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding
This paper describes a dynamic voltage and frequency scaling (DVFS) technique for MPEG decoding to reduce the energy consumption using the computational workload decomposition. Th...
Kihwan Choi, Ramakrishna Soma, Massoud Pedram
PERCOM
2009
ACM
14 years 2 months ago
TreeMAC: Localized TDMA MAC Protocol for Real-time High-data-rate Sensor Networks
—Earlier sensor network MAC protocols focus on energy conservation in low-duty cycle applications, while some recent applications involve real-time high-data-rate signals. This m...
Wen-Zhan Song, Renjie Huang, Behrooz Shirazi, Rich...