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» The design of a low energy FPGA
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IWCMC
2006
ACM
14 years 21 days ago
Budgeting power: packet duplication and bit error rate reduction in wireless ad-hoc networks
In this paper we present and evaluate a new technique to lower packet-level error rates of application layer connections in wireless ad-hoc networks. In our scheme, data packets s...
Ghassen Ben Brahim, Bilal Khan
CASES
2007
ACM
13 years 10 months ago
Cache leakage control mechanism for hard real-time systems
Leakage energy consumption is an increasingly important issue as the technology continues to shrink. Since on-chip caches constitute a major portion of the processor's transi...
Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia...
TC
2008
13 years 6 months ago
Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
MONET
2007
126views more  MONET 2007»
13 years 6 months ago
Performance Evaluation of a Power Management Scheme for Disruption Tolerant Network
Disruption Tolerant Network (DTN) is characterized by frequent partitions and intermittent connectivity. Power management issue in such networks is challenging. Existing power man...
Yong Xi, Mooi Choo Chuah, K. Chang
MOBIHOC
2004
ACM
14 years 4 days ago
A message ferrying approach for data delivery in sparse mobile ad hoc networks
Mobile Ad Hoc Networks (MANETs) provide rapidly deployable and self-configuring network capacity required in many critical applications, e.g., battlefields, disaster relief and ...
Wenrui Zhao, Mostafa H. Ammar, Ellen W. Zegura