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» The dynamic granularity memory system
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HIPEAC
2009
Springer
14 years 3 months ago
HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic
Abstract. Exposing more instruction-level parallelism in out-of-order superscalar processors requires increasing the number of dynamic in-flight instructions. However, large instru...
Suriya Subramanian, Kathryn S. McKinley
PLDI
2012
ACM
12 years 1 months ago
Speculative separation for privatization and reductions
Automatic parallelization is a promising strategy to improve application performance in the multicore era. However, common programming practices such as the reuse of data structur...
Nick P. Johnson, Hanjun Kim, Prakash Prabhu, Ayal ...
USENIX
1993
14 years 13 days ago
Linking Shared Segments
As an alternative to communication via messages or files, shared memory has the potential to be simpler, faster, and less wasteful of space. Unfortunately, the mechanisms availab...
W. E. Garrett, Michael L. Scott, Ricardo Bianchini...
IISWC
2006
IEEE
14 years 5 months ago
Modeling Cache Sharing on Chip Multiprocessor Architectures
— As CMPs are emerging as the dominant architecture for a wide range of platforms (from embedded systems and game consoles, to PCs, and to servers) the need to manage on-chip res...
Pavlos Petoumenos, Georgios Keramidas, Håkan...
DATE
1998
IEEE
153views Hardware» more  DATE 1998»
14 years 3 months ago
An Energy-Conscious Exploration Methodology for Reconfigurable DSPs
As the "system-on-a-chip" concept is rapidly becoming a reality, time-to-market and product complexity push the reuse of complex macromodules. Circuits combining a varie...
Jan M. Rabaey, Marlene Wan