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TPDS
2010
174views more  TPDS 2010»
13 years 9 months ago
Parallel Two-Sided Matrix Reduction to Band Bidiagonal Form on Multicore Architectures
The objective of this paper is to extend, in the context of multicore architectures, the concepts of tile algorithms [Buttari et al., 2007] for Cholesky, LU, QR factorizations to t...
Hatem Ltaief, Jakub Kurzak, Jack Dongarra
TVLSI
2008
157views more  TVLSI 2008»
13 years 11 months ago
Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory
This paper proposes a high-performance scalable quality-of-service (QoS)-aware memory controller for the packet memory where packet data are stored in network routers. A major chal...
Hyuk-Jun Lee, Eui-Young Chung
ICDIM
2008
IEEE
14 years 5 months ago
A holographic associative memory recommender system
We describe a recommender system based on Dynamically Structured Holographic Memory (DSHM), a cognitive model of associative memory that uses holographic reduced representations a...
Matthew Rutledge-Taylor, Andre Vellino, Robert L. ...
ASPLOS
2006
ACM
14 years 2 months ago
Efficient type and memory safety for tiny embedded systems
We report our experience in implementing type and memory safety in an efficient manner for sensor network nodes running TinyOS: tiny embedded systems running legacy, C-like code. ...
John Regehr, Nathan Cooprider, Will Archer, Eric E...
HIPC
2007
Springer
14 years 5 months ago
Self-optimization of Performance-per-Watt for Interleaved Memory Systems
- With the increased complexity of platforms coupled with data centers’ servers sprawl, power consumption is reaching unsustainable limits. Memory is an important target for plat...
Bithika Khargharia, Salim Hariri, Mazin S. Yousif