The objective of this paper is to extend, in the context of multicore architectures, the concepts of tile algorithms [Buttari et al., 2007] for Cholesky, LU, QR factorizations to t...
This paper proposes a high-performance scalable quality-of-service (QoS)-aware memory controller for the packet memory where packet data are stored in network routers. A major chal...
We describe a recommender system based on Dynamically Structured Holographic Memory (DSHM), a cognitive model of associative memory that uses holographic reduced representations a...
Matthew Rutledge-Taylor, Andre Vellino, Robert L. ...
We report our experience in implementing type and memory safety in an efficient manner for sensor network nodes running TinyOS: tiny embedded systems running legacy, C-like code. ...
John Regehr, Nathan Cooprider, Will Archer, Eric E...
- With the increased complexity of platforms coupled with data centers’ servers sprawl, power consumption is reaching unsustainable limits. Memory is an important target for plat...