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GECCO
2007
Springer
300views Optimization» more  GECCO 2007»
14 years 1 months ago
A NSGA-II, web-enabled, parallel optimization framework for NLP and MINLP
Engineering design increasingly uses computer simulation models coupled with optimization algorithms to find the best design that meets the customer constraints within a time con...
David J. Powell, Joel K. Hollingsworth
DAC
2006
ACM
14 years 8 months ago
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors i...
John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S....
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
11 years 10 months ago
BlockChop: Dynamic squash elimination for hybrid processor architecture
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
Jason Mars, Naveen Kumar
DEXAW
2003
IEEE
122views Database» more  DEXAW 2003»
14 years 25 days ago
A Framework for Self-Optimizing Grids Using P2P Components
We present the framework of a new grid architecture based on the peer-to-peer and the component paradigms. In our architecture, several peer-to-peer components are loosely coupled...
Florian Schintke, Thorsten Schütt, Alexander ...
ERSA
2008
185views Hardware» more  ERSA 2008»
13 years 9 months ago
Design Framework for Partial Run-Time FPGA Reconfiguration
Partial reconfiguration (PR) reveals many opportunities for integration into FPGA design for potential system optimizations such as reduced area, increased performance, and increa...
Chris Conger, Ann Gordon-Ross, Alan D. George