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DATE
2005
IEEE
128views Hardware» more  DATE 2005»
14 years 2 months ago
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected b...
Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Ca...
DATE
2005
IEEE
129views Hardware» more  DATE 2005»
14 years 2 months ago
Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling
A novel energy reduction strategy to maximally exploit the dynamic workload variation is proposed for the offline voltage scheduling of preemptive systems. The idea is to construc...
Lap-Fai Leung, Chi-Ying Tsui, Xiaobo Sharon Hu
DATE
2005
IEEE
88views Hardware» more  DATE 2005»
14 years 2 months ago
System Synthesis for Networks of Programmable Blocks
The advent of sensor networks presents untapped opportunities for synthesis. We examine the problem of synthesis of behavioral specifications into networks of programmable sensor ...
Ryan Mannion, Harry Hsieh, Susan Cotterell, Frank ...
FOCS
2002
IEEE
14 years 1 months ago
Learning a Hidden Matching
We consider the problem of learning a matching (i.e., a graph in which all vertices have degree 0 or 1) in a model where the only allowed operation is to query whether a set of ve...
Noga Alon, Richard Beigel, Simon Kasif, Steven Rud...
DATE
2008
IEEE
122views Hardware» more  DATE 2008»
14 years 3 months ago
Digital bit stream jitter testing using jitter expansion
This paper presents a time-domain jitter expansion technique for high-speed digital bit sequence jitter testing. While jitter expansion has been applied to phase noise measurement...
Hyun Choi, Abhijit Chatterjee