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MICRO
1999
IEEE
115views Hardware» more  MICRO 1999»
13 years 12 months ago
Fetch Directed Instruction Prefetching
Instruction supply is a crucial component of processor performance. Instruction prefetching has been proposed as a mechanism to help reduce instruction cache misses, which in turn...
Glenn Reinman, Brad Calder, Todd M. Austin
ASAP
2007
IEEE
133views Hardware» more  ASAP 2007»
13 years 11 months ago
An Efficient Hardware Support for Control Data Validation
Software-based, fine-grain control flow integrity (CFI) validation technique has been proposed to enforce control flow integrity of program execution. By validating every indirect...
Yong-Joon Park, Zhao Zhang, Gyungho Lee
ISHPC
2000
Springer
13 years 11 months ago
Loop Termination Prediction
Deeply pipelined high performance processors require highly accurate branch prediction to drive their instruction fetch. However there remains a class of events which are not easi...
Timothy Sherwood, Brad Calder
BMCBI
2004
111views more  BMCBI 2004»
13 years 7 months ago
The Hotdog fold: wrapping up a superfamily of thioesterases and dehydratases
Background: The Hotdog fold was initially identified in the structure of Escherichia coli FabA and subsequently in 4-hydroxybenzoyl-CoA thioesterase from Pseudomonas sp. strain CB...
Shane C. Dillon, Alex Bateman
ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
13 years 11 months ago
Instruction Cache Fetch Policies for Speculative Execution
Current trends in processor design are pointing to deeper and wider pipelines and superscalar architectures. The efficient use of these resources requires speculative execution, ...
Dennis Lee, Jean-Loup Baer, Brad Calder, Dirk Grun...