431 search results - page 50 / 87 » The predictability of branches in libraries |
ICS
1998
Tsinghua U.
13 years 11 months ago
1998
Tsinghua U.
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
HPCA
2003
IEEE
14 years 8 months ago
2003
IEEE
Although caches for decades have been the backbone of the memory system, the speed gap between CPU and main memory suggests their augmentation with prefetching mechanisms. Recentl...
ICS
2007
Tsinghua U.
14 years 1 months ago
2007
Tsinghua U.
This paper investigates helper threads that improve performance by prefetching data on behalf of an application’s main thread. The focus is data prefetch helper threads that lac...
ISCA
1999
IEEE
13 years 12 months ago
1999
IEEE
The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buffering and reusing dynamic instruction traces. This work presents a new block-b...
CCS
2007
ACM
14 years 1 months ago
2007
ACM
Abstract. MicroArchitectural Attacks (MA), which can be considered as a special form of SideChannel Analysis, exploit microarchitectural functionalities of processor implementation...