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MICRO
1993
IEEE
131views Hardware» more  MICRO 1993»
13 years 11 months ago
Superblock formation using static program analysis
Compile-time code transformations which expose instruction-level parallelism (ILP) typically take into account the constraints imposed by all execution scenarios in the program. H...
Richard E. Hank, Scott A. Mahlke, Roger A. Bringma...
DATE
2004
IEEE
184views Hardware» more  DATE 2004»
13 years 11 months ago
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
We show how to automatically verify that complex XScale-like pipelined machine models satisfy the same safety and liveness properties as their corresponding instruction set archit...
Panagiotis Manolios, Sudarshan K. Srinivasan
EUROPAR
2000
Springer
13 years 11 months ago
On the Performance of Fetch Engines Running DSS Workloads
Abstract This paper examines the behavior of current and next generation microprocessors' fetch engines while running Decision Support Systems (DSS) workloads. We analyze the ...
Carlos Navarro, Alex Ramírez, Josep-Lluis L...
ISCA
1995
IEEE
133views Hardware» more  ISCA 1995»
13 years 11 months ago
Performance Evaluation of the PowerPC 620 Microarchitecture
The PowerPC 620TM microprocessor1 is the most recent and performance leading member of the PowerPCTM family. The 64-bit PowerPC 620 microprocessor employs a two-phase branch predi...
Trung A. Diep, Christopher Nelson, John Paul Shen
BIOSYSTEMS
2008
100views more  BIOSYSTEMS 2008»
13 years 7 months ago
Objective patterns in the evolving network of non-equivalent observers
The world's objective pattern is formed through consistent histories of quantum measurements originating as different branches of the same wave function. When we come close t...
Abir U. Igamberdiev