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ASPDAC
2005
ACM
113views Hardware» more  ASPDAC 2005»
15 years 10 months ago
Scalable interprocedural register allocation for high level synthesis
Abstract— The success of classical high level synthesis has been limited by the complexity of the applications it can handle, typically not large enough to necessitate the depart...
Rami Beidas, Jianwen Zhu
CHES
2005
Springer
155views Cryptology» more  CHES 2005»
15 years 10 months ago
Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization
Motivated by the goal of factoring large integers using the Number Field Sieve, several special-purpose hardware designs have been recently proposed for solving large sparse system...
Willi Geiselmann, Adi Shamir, Rainer Steinwandt, E...
SIGCOMM
1998
ACM
15 years 8 months ago
Fast and Scalable Layer Four Switching
In Layer Four switching, the route and resources allocated to a packet are determined by the destination address as well as other header elds of the packet such as source address,...
Venkatachary Srinivasan, George Varghese, Subhash ...
ICPP
1990
IEEE
15 years 8 months ago
Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes
As multiprocessors are scaled beyond single bus systems, there is renewed interest in directory-based cache coherence schemes. These schemes rely on a directory to keep track of a...
Anoop Gupta, Wolf-Dietrich Weber, Todd C. Mowry
FASE
2006
Springer
15 years 8 months ago
: Designing a Scalable Build Process
Modern software codebases are frequently large, heterogeneous, and constantly evolving. The languages and tools for software construction, including code builds and configuration m...
Jason Hickey, Aleksey Nogin