98 search results - page 12 / 20 » The scaling of interconnect buffer needs |
ASYNC
2005
IEEE
14 years 1 months ago
2005
IEEE
Networks on Chip that can guarantee Quality of Service (QNoC) are based on special routers that can support multiple service levels. GALS SoCs call for asynchronous NoC implementa...
WMPI
2004
ACM
14 years 29 days ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
VLDB
2001
ACM
13 years 12 months ago
2001
ACM
Cache Fusion TM is a fundamental component of Oracle’s Real Application Cluster configuration, a shared-cache clustered-database architecture that transparently extends databas...
ISQED
2008
IEEE
14 years 1 months ago
2008
IEEE
– As silicon technology scales, we can integrate more and more circuits on a single chip, which means more I/Os are needed in modern designs. The flip-chip technology which was ...
SIGCOMM
2003
ACM
14 years 24 days ago
2003
ACM
Routers built around a single-stage crossbar and a centralized scheduler do not scale, and (in practice) do not provide the throughput guarantees that network operators need to ma...