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» The scaling of interconnect buffer needs
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JSAC
2008
94views more  JSAC 2008»
13 years 7 months ago
Detection, Synchronization, and Doppler Scale Estimation with Multicarrier Waveforms in Underwater Acoustic Communication
In this paper, we propose a novel method for detection, synchronization and Doppler scale estimation for underwater acoustic communication using orthogonal frequency division multi...
Sean F. Mason, Christian R. Berger, Shengli Zhou, ...
MICRO
2003
IEEE
108views Hardware» more  MICRO 2003»
14 years 25 days ago
Reducing Design Complexity of the Load/Store Queue
With faster CPU clocks and wider pipelines, all relevant microarchitecture components should scale accordingly. There have been many proposals for scaling the issue queue, registe...
Il Park, Chong-liang Ooi, T. N. Vijaykumar
GLVLSI
2005
IEEE
104views VLSI» more  GLVLSI 2005»
14 years 1 months ago
Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing
The ever-increasing number of transistors on a chip has resulted in very large scale integration (VLSI) systems whose performance and manufacturing costs are driven by on-chip wir...
Ajay Joshi, Jeffrey A. Davis
ICC
2007
IEEE
138views Communications» more  ICC 2007»
14 years 1 months ago
Scalable Router Memory Architecture Based on Inter-leaved DRAM: Analysis and Numerical Studies
1  Routers need buffers to store and forward packets, especially when there is network congestion. With current memory technology, neither the SRAM nor the DRAM alone is suitabl...
Feng Wang, Mounir Hamdi
AISC
2010
Springer
14 years 11 days ago
Towards MKM in the Large: Modular Representation and Scalable Software Architecture
Abstract. MKM has been defined as the quest for technologies to manage mathematical knowledge. MKM “in the small” is well-studied, so the real problem is to scale up to large,...
Michael Kohlhase, Florian Rabe, Vyacheslav Zholude...