Sciweavers

98 search results - page 5 / 20
» The scaling of interconnect buffer needs
Sort
View
ISCAS
2005
IEEE
159views Hardware» more  ISCAS 2005»
14 years 1 months ago
A low power FPGA routing architecture
— Significant headway has been made in logic density and performance of FPGAs in the past decade. Power efficiency of FPGA architectures is arguably the next most important crite...
Somsubhra Mondal, Seda Ogrenci Memik
DAC
2006
ACM
14 years 8 months ago
Are carbon nanotubes the future of VLSI interconnections?
Increasing resistivity of copper with scaling and rising demands on current density requirements are driving the need to identify new wiring solutions for deep nanometer scale VLS...
Kaustav Banerjee, Navin Srivastava
DSD
2008
IEEE
136views Hardware» more  DSD 2008»
14 years 2 months ago
Network Interface Sharing Techniques for Area Optimized NoC Architectures
Although preliminary analysis frameworks point out the performance speed-ups achievable by on-chip networks with respect to state-of-the-art interconnects, the area concern remain...
Alberto Ferrante, Simone Medardoni, Davide Bertozz...
DAC
2005
ACM
14 years 8 months ago
Net weighting to reduce repeater counts during placement
We demonstrate how to use placement to ameliorate the predicted repeater explosion problem caused by poor interconnect scaling. We achieve repeater count reduction by dynamically ...
Brent Goplen, Prashant Saxena, Sachin S. Sapatneka...
ANSS
2001
IEEE
13 years 11 months ago
New Queuing Strategy for Large Scale ATM Switches
In this work, we study the different buffering techniques used in the literature to solve the contention problem in A TM switching architectures. The objective of our study is to ...
Mohsen Guizani, Ala I. Al-Fuqaha