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ICS
2005
Tsinghua U.
14 years 1 months ago
2005
Tsinghua U.
Excessive power consumption is becoming a major barrier to extracting the maximum performance from high-performance parallel systems. Therefore, techniques oriented towards reduci...
LCTRTS
1999
Springer
13 years 12 months ago
1999
Springer
Code space is a critical issue facing designers of software for embedded systems. Many traditional compiler optimizations are designed to reduce the execution time of compiled cod...
CF
2004
ACM
13 years 11 months ago
2004
ACM
Off-chip memory accesses are a major source of power consumption in embedded processors. In order to reduce the amount of traffic between the processor and the off-chip memory as ...
NETWORKING
2010
13 years 6 months ago
2010
Web caching techniques reduce user-perceived latency by serving the most popular web objects from an intermediate memory. In order to assure that reused objects are not stale, cond...
HPCA
2005
IEEE
14 years 8 months ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...