This paper describes a two-state methodology for register transfer level (RTL) logic simulation in which the use of the Xstate is completely eliminated inside ASIC designs. Exampl...
This paper reviews the performance of various methods used to detect the warm up length in steady state discrete event simulation. An evaluation procedure is used to compare the m...
In this paper, we address the complex task of initializing an on-line simulation to a current system state collected from an operating physical system. The paper begins by discuss...
– This paper describes a new technique for extracting clock-level finite state machines(FSMs) from transistor netlists using symbolic simulation. The transistor netlist is prepr...
Manish Pandey, Alok Jain, Randal E. Bryant, Derek ...
This paper introduces minimal subset evaluation (MSE) as a way to reduce time spent on large-structure warm-up during the fastforwarding portion of processor simulations. Warm up ...