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DAC
1999
ACM
13 years 11 months ago
A Two-State Methodology for RTL Logic Simulation
This paper describes a two-state methodology for register transfer level (RTL) logic simulation in which the use of the Xstate is completely eliminated inside ASIC designs. Exampl...
Lionel Bening
WSC
2004
13 years 8 months ago
Evaluation of Methods Used to Detect Warm-Up Period in Steady State Simulation
This paper reviews the performance of various methods used to detect the warm up length in steady state discrete event simulation. An evaluation procedure is used to compare the m...
Prasad S. Mahajan, Ricki G. Ingalls
WSC
1998
13 years 8 months ago
Initializing On-line Simulations from the State of a Distributed System
In this paper, we address the complex task of initializing an on-line simulation to a current system state collected from an operating physical system. The paper begins by discuss...
Fernando G. Gonzalez, Wayne J. Davis
ICCD
1995
IEEE
119views Hardware» more  ICCD 1995»
13 years 11 months ago
Extraction of finite state machines from transistor netlists by symbolic simulation
– This paper describes a new technique for extracting clock-level finite state machines(FSMs) from transistor netlists using symbolic simulation. The transistor netlist is prepr...
Manish Pandey, Alok Jain, Randal E. Bryant, Derek ...
ICCD
2001
IEEE
77views Hardware» more  ICCD 2001»
14 years 4 months ago
Minimal Subset Evaluation: Rapid Warm-Up for Simulated Hardware State
This paper introduces minimal subset evaluation (MSE) as a way to reduce time spent on large-structure warm-up during the fastforwarding portion of processor simulations. Warm up ...
John W. Haskins Jr., Kevin Skadron