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IPPS
1997
IEEE
15 years 8 months ago
A Reliable Hardware Barrier Synchronization Scheme
Barrier synchronization is a crucial operation for parallel systems. Many schemes have been proposed in the literature to achieve fast barrier synchronization through software, ha...
Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. P...
TCAD
2010
103views more  TCAD 2010»
14 years 11 months ago
Supervised Learning Based Power Management for Multicore Processors
- This paper presents a supervised learning based power management framework for a multi-processor system, where a power manager (PM) learns to predict the system performance state...
Hwisung Jung, Massoud Pedram
CASES
2004
ACM
15 years 10 months ago
Procedure placement using temporal-ordering information: dealing with code size expansion
Abstract— In a direct-mapped instruction cache, all instructions that have the same memory address modulo the cache size, share a common and unique cache slot. Instruction cache ...
Christophe Guillon, Fabrice Rastello, Thierry Bida...
GECCO
2008
Springer
172views Optimization» more  GECCO 2008»
15 years 5 months ago
Empirical analysis of a genetic algorithm-based stress test technique
Evolutionary testing denotes the use of evolutionary algorithms, e.g., Genetic Algorithms (GAs), to support various test automation tasks. Since evolutionary algorithms are heuris...
Vahid Garousi
DATE
2006
IEEE
115views Hardware» more  DATE 2006»
15 years 10 months ago
Management of complex automotive communication networks
Automakers are still facing an increasing complexity in vehicle requirements with regard to their EE systems. This complexity is not only caused by innovations, which are being pr...
Thomas Weber