145 search results - page 3 / 29 » The use of random simulation in formal verification |
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...
DSD
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper proposes a validation approach, based on simulation, which addresses problems related to both state space explosion of formal methods and low coverage of informal metho...
FMCAD
2007
Springer
14 years 1 months ago
2007
Springer
— The concept of applying partial fencing to logic built-in self test (LBIST) hardware structures for the purpose of using partially good chips is well known in the chip design i...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
ICCAD
2000
IEEE
14 years 7 hour ago
2000
IEEE
computation and automatic abstraction. Second, Ketchum performs not only automatic test generation but also unreachability analysis, which enables the test generation effort to be ...