145 search results - page 5 / 29 » The use of random simulation in formal verification |
HASE
2008
IEEE
13 years 7 months ago
2008
IEEE
Designing safety-critical systems is a complex process, and especially when the design is carried out at different f abstraction where the correctness of the design at one level i...
TVLSI
2008
13 years 7 months ago
2008
ion levels. The framework also supports the generation of test constraints, which can be satisfied using a constraint solver to generate tests. A compositional verification approac...
CAV
2006
Springer
13 years 11 months ago
2006
Springer
We describe a formal verification of a recent concurrent list-based set algorithm due to Heller et al. The algorithm is optimistic: the add and remove operations traverse the list ...
FORMATS
2006
Springer
13 years 11 months ago
2006
Springer
In this paper, we consider a novel approach to the temporal logic verification problem of continuous dynamical systems. Our methodology has the distinctive feature that enables the...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...