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» The use of random simulation in formal verification
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RTCSA
1997
IEEE
13 years 11 months ago
Behavior verification of hybrid real-time requirements by qualitative formalism
Although modern control theories have been successfully applied to solve a variety of problems, they are often mathematically and physically too specific to describe and analyze t...
Jang-Soo Lee, Sung Deok Cha
FMCAD
2007
Springer
13 years 11 months ago
Combining Symbolic Simulation and Interval Arithmetic for the Verification of AMS Designs
Abstract--Analog and mixed signal (AMS) designs are important integrated circuits that are usually needed at the interface between the electronic system and the real world. Recentl...
Mohamed H. Zaki, Ghiath Al Sammane, Sofiène...
DAC
2002
ACM
14 years 8 months ago
Deriving a simulation input generator and a coverage metric from a formal specification
This paper presents novel uses of functional interface specifications for verifying RTL designs. We demonstrate how a simulation environment, a correctness checker, and a function...
Kanna Shimizu, David L. Dill
TCAD
2002
121views more  TCAD 2002»
13 years 7 months ago
Robust Boolean reasoning for equivalence checking and functional property verification
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...
Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, ...
ASPDAC
2004
ACM
94views Hardware» more  ASPDAC 2004»
13 years 11 months ago
Improving simulation-based verification by means of formal methods
The design of complex systems is largely ruled by the time needed for verification. Even though formal methods can provide higher reliability, in practice often simulation based ve...
Görschwin Fey, Rolf Drechsler