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ISCAS
2008
IEEE
134views Hardware» more  ISCAS 2008»
14 years 1 months ago
Bidirectionally decodable Wyner-Ziv video coding
Abstract— Inter frame prediction technique significantly improves the compression efficiency in the hybrid video coding schemes. However, this technique causes the decoding dep...
Xiaopeng Fan, Oscar C. Au, Yan Chen, Jiantao Zhou,...
MICRO
2008
IEEE
159views Hardware» more  MICRO 2008»
14 years 1 months ago
A novel cache architecture with enhanced performance and security
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
Zhenghong Wang, Ruby B. Lee
EUROCRYPT
2007
Springer
14 years 1 months ago
Feistel Networks Made Public, and Applications
Feistel Network, consisting of a repeated application of the Feistel Transform, gives a very convenient and popular method for designing “cryptographically strong” permutations...
Yevgeniy Dodis, Prashant Puniya
DATE
2006
IEEE
101views Hardware» more  DATE 2006»
14 years 1 months ago
Design with race-free hardware semantics
Most hardware description languages do not enforce determinacy, meaning that they may yield races. Race conditions pose a problem for the implementation, verification, and validat...
Patrick Schaumont, Sandeep K. Shukla, Ingrid Verba...
GLVLSI
2006
IEEE
152views VLSI» more  GLVLSI 2006»
14 years 1 months ago
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...
Rashed Zafar Bhatti, Monty Denneau, Jeff Draper