Sciweavers

146 search results - page 26 / 30
» Thread Level Parallelism and Interactive Performance of Desk...
Sort
View
SPAA
2009
ACM
14 years 8 months ago
A lightweight in-place implementation for software thread-level speculation
Thread-level speculation (TLS) is a technique that allows parts of a sequential program to be executed in parallel. TLS ensures the parallel program's behaviour remains true ...
Cosmin E. Oancea, Alan Mycroft, Tim Harris
GRID
2008
Springer
13 years 7 months ago
Scheduling for Responsive Grids
Grids are facing the challenge of seamless integration of the grid power into everyday use. One critical component for this integration is responsiveness, the capacity to support o...
Cécile Germain-Renaud, Charles Loomis, Jaku...
CLUSTER
2009
IEEE
13 years 11 months ago
Using a cluster as a memory resource: A fast and large virtual memory on MPI
—The 64-bit OS provides ample memory address space that is beneficial for applications using a large amount of data. This paper proposes using a cluster as a memory resource for...
Hiroko Midorikawa, Kazuhiro Saito, Mitsuhisa Sato,...
VIS
2009
IEEE
200views Visualization» more  VIS 2009»
14 years 9 months ago
Interactive Coordinated Multiple-View Visualization of Biomechanical Motion Data
Abstract-- We present an interactive framework for exploring space-time relationships in databases of experimentally collected highresolution biomechanical data. These data describ...
Daniel F. Keefe, Marcus Ewert, William Ribarsky,...
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 5 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt