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PDP
2011
IEEE
13 years 2 months ago
Quantifying Thread Vulnerability for Multicore Architectures
Abstract—Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, mu...
Isil Oz, Haluk Rahmi Topcuoglu, Mahmut T. Kandemir...
HPCA
2006
IEEE
14 years 10 months ago
An approach for implementing efficient superscalar CISC processors
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E...
CASES
2006
ACM
14 years 4 months ago
Mitigating soft error failures for multimedia applications by selective data protection
With advances in process technology, soft errors (SE) are becoming an increasingly critical design concern. Due to their large area and high density, caches are worst hit by soft ...
Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, N...
HIPEAC
2009
Springer
14 years 3 months ago
Revisiting Cache Block Superloading
Abstract. Technological advances and increasingly complex and dynamic application behavior argue for revisiting mechanisms that adapt logical cache block size to application charac...
Matthew A. Watkins, Sally A. McKee, Lambert Schael...
CODES
2008
IEEE
14 years 4 months ago
Distributed and low-power synchronization architecture for embedded multiprocessors
In this paper we present a framework for a distributed and very low-cost implementation of synchronization controllers and protocols for embedded multiprocessors. The proposed arc...
Chenjie Yu, Peter Petrov