Sciweavers

248 search results - page 7 / 50
» Threaded Multiple Path Execution
Sort
View
ICS
2001
Tsinghua U.
14 years 1 months ago
Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor
Recent proposals for Chip Multiprocessors (CMPs) advocate speculative, or implicit, threading in which the hardware employs prediction to peel off instruction sequences (i.e., imp...
Chong-liang Ooi, Seon Wook Kim, Il Park, Rudolf Ei...
ISCA
2010
IEEE
185views Hardware» more  ISCA 2010»
14 years 1 months ago
Dynamic warp subdivision for integrated branch and memory divergence tolerance
SIMD organizations amortize the area and power of fetch, decode, and issue logic across multiple processing units in order to maximize throughput for a given area and power budget...
Jiayuan Meng, David Tarjan, Kevin Skadron
MICRO
2010
IEEE
210views Hardware» more  MICRO 2010»
13 years 6 months ago
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior
In a modern chip-multiprocessor system, memory is a shared resource among multiple concurrently executing threads. The memory scheduling algorithm should resolve memory contention...
Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor H...
MICRO
2011
IEEE
407views Hardware» more  MICRO 2011»
13 years 3 months ago
Thread Cluster Memory Scheduling
In a modern chip-multiprocessor system, memory is a shared resource among multiple concurrently executing threads. The memory scheduling algorithm should resolve memory contention...
Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor H...
SOSP
1989
ACM
13 years 9 months ago
Threads and Input/Output in the Synthesis Kernel
The Synthesis operating system kernel combines several techniques to provide high performa.nce, incl1iding kernel code synthesis, fine-gra.in scheduling. and optimistic sylicllrol...
Henry Massalin, Calton Pu