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GLVLSI
2003
IEEE
132views VLSI» more  GLVLSI 2003»
14 years 3 months ago
Power-aware pipelined multiplier design based on 2-dimensional pipeline gating
Power-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Multipliers are essential elements used in DSP applications and c...
Jia Di, Jiann S. Yuan
GLVLSI
2003
IEEE
177views VLSI» more  GLVLSI 2003»
14 years 3 months ago
Congestion reduction in traditional and new routing architectures
In dense integrated circuit designs, management of routing congestion is essential; an over congested design may be unroutable. Many factors influence congestion: placement, rout...
Ameya R. Agnihotri, Patrick H. Madden
GLVLSI
2003
IEEE
140views VLSI» more  GLVLSI 2003»
14 years 3 months ago
Exploiting multiple functionality for nano-scale reconfigurable systems
It is likely that it will become increasingly difficult to manufacture the complex, heterogeneous logic structures that characterise current reconfigurable logic systems. As a res...
Paul Beckett
GLVLSI
2003
IEEE
310views VLSI» more  GLVLSI 2003»
14 years 3 months ago
54x54-bit radix-4 multiplier based on modified booth algorithm
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...
Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-se...
GLVLSI
2003
IEEE
173views VLSI» more  GLVLSI 2003»
14 years 3 months ago
40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applications
An embedded 40 MHz FIFO buffer for use in mixed-signal information processing applications is presented. The buffer design uses a 1T DRAM topology for its unit memory cell compone...
Michael I. Fuller, James P. Mabry, John A. Hossack...