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ERSA
2006
186views Hardware» more  ERSA 2006»
13 years 9 months ago
The Case for High Level Programming Models for Reconfigurable Computers
In this paper we first outline and discuss the issues of currently accepted computational models for hybrid CPU/FPGA systems. Then, we discuss the need for researchers to develop ...
David L. Andrews, Ron Sass, Erik Anderson, Jason A...
ICCD
2007
IEEE
150views Hardware» more  ICCD 2007»
13 years 11 months ago
CAP: Criticality analysis for power-efficient speculative multithreading
While Speculative Multithreading (SM) on a Chip Multiprocessor (CMP) has the ability to speed-up hard-toparallelize applications, the power inefficiency of aggressive speculation ...
James Tuck, Wei Liu, Josep Torrellas
IFE
2010
87views more  IFE 2010»
13 years 5 months ago
A middleware for efficient stream processing in CUDA
This paper presents a middleware capable of out-of-order execution of kernels and data transfers for efficient stream processing in the compute unified device architecture (CUDA). ...
Shinta Nakagawa, Fumihiko Ino, Kenichi Hagihara
ICDCS
2002
IEEE
14 years 19 days ago
An Extensible and Scalable Content Adaptation Pipeline Architecture to Support Heterogeneous Clients
The importance of middleware and content adaptation has previously been demonstrated for pervasive use of Web-based applications. In this paper we propose a modular, extensible, a...
Thomas Phan, George Zorpas, Rajive Bagrodia
EUROPAR
2010
Springer
13 years 7 months ago
Optimized On-Chip-Pipelined Mergesort on the Cell/B.E
Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even mor...
Rikard Hultén, Christoph W. Kessler, Jö...