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» Tight bounds for clock synchronization
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CODES
2008
IEEE
13 years 9 months ago
Performance debugging of Esterel specifications
Synchronous languages like Esterel have been widely adopted for designing reactive systems in safety-critical domains such as avionics. Specifications written in Esterel are based...
Lei Ju, Bach Khoa Huynh, Abhik Roychoudhury, Samar...
PARELEC
2002
IEEE
14 years 17 days ago
Real-Time Scheduling in Distributed Systems
In this paper, we investigate the worst case performance of Earliest Due Date algorithm when applied to packet scheduling in distributed systems. We assume that the processing ele...
Nguyen Duc Thai
SASO
2007
IEEE
14 years 1 months ago
Desynchronization: The Theory of Self-Organizing Algorithms for Round-Robin Scheduling
The study of synchronization has received much attention in a variety of applications, ranging from coordinating sensors in wireless networks to models of fireflies flashing in...
Ankit Patel, Julius Degesys, Radhika Nagpal
ASYNC
2002
IEEE
120views Hardware» more  ASYNC 2002»
14 years 19 days ago
Relative Timing Based Verification of Timed Circuits and Systems
Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...
Peter A. Beerel, Ken S. Stevens, Hoshik Kim
CONCUR
1999
Springer
13 years 12 months ago
Partial Order Reduction for Model Checking of Timed Automata
Abstract. The paper presents a partial order reduction method applicable to networks of timed automata. The advantage of the method is that it reduces both the number of explored c...
Marius Minea