13 search results - page 3 / 3 » Tile Size Selection Using Cache Organization and Data Layout |
ISCA
2010
IEEE
14 years 16 days ago
2010
IEEE
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...
VIS
2007
IEEE
14 years 8 months ago
2007
IEEE
With the exponential growth in size of geometric data, it is becoming increasingly important to make effective use of multilevel caches, limited disk storage, and bandwidth. As a r...
SCOPES
2004
Springer
14 years 24 days ago
2004
Springer
For mobile embedded systems, the energy consumption is a limiting factor because of today’s battery capacities. Besides the processor, memory accesses consume a high amount of en...