Planning based on propositional SAT(isfiability) is a powerful approach to computing step-optimal plans given a parallel execution semantics. In this setting: (i) a solution plan ...
Nathan Robinson, Charles Gretton, Duc Nghia Pham, ...
In deep submicron technology, IR-drop and clock skew issues become more crucial to the functionality of chip. This paper presents a oorplan-based power and clock distribution meth...
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Multimedia Broadcast Multicast Services (MBMS), introduced in Third Generation Partnership Project (3GPP) Release 6, is a point-to-multipoint downlink bearer service that addresse...
Antonios G. Alexiou, Christos Bouras, Vasileios Ko...
— Robust power distribution within available routing area resources is critical to chip performance and reliability. In this paper, we propose a novel and efficient method for o...
Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ma...