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AIPS
2009
13 years 8 months ago
SAT-Based Parallel Planning Using a Split Representation of Actions
Planning based on propositional SAT(isfiability) is a powerful approach to computing step-optimal plans given a parallel execution semantics. In this setting: (i) a solution plan ...
Nathan Robinson, Charles Gretton, Duc Nghia Pham, ...
DAC
1999
ACM
14 years 2 days ago
A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs
In deep submicron technology, IR-drop and clock skew issues become more crucial to the functionality of chip. This paper presents a oorplan-based power and clock distribution meth...
Joon-Seo Yim, Seong-Ok Bae, Chong-Min Kyung
ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
ISCC
2007
IEEE
109views Communications» more  ISCC 2007»
14 years 2 months ago
MBMS Power Planning in Macro and Micro Cell Environments
Multimedia Broadcast Multicast Services (MBMS), introduced in Third Generation Partnership Project (3GPP) Release 6, is a point-to-multipoint downlink bearer service that addresse...
Antonios G. Alexiou, Christos Bouras, Vasileios Ko...
ASPDAC
2004
ACM
148views Hardware» more  ASPDAC 2004»
14 years 1 months ago
Optimal planning for mesh-based power distribution
— Robust power distribution within available routing area resources is critical to chip performance and reliability. In this paper, we propose a novel and efficient method for o...
Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ma...