41 search results - page 4 / 9 » Tiling layouts with dominoes |
FPGA
2003
ACM
14 years 17 days ago
2003
ACM
One of the most difficult and time-consuming steps in the creation of an FPGA is its transistor-level design and physical layout. Modern commercial FPGAs typically consume anywher...
PLDI
1995
ACM
13 years 11 months ago
1995
ACM
When dense matrix computations are too large to fit in cache, previous research proposes tiling to reduce or eliminate capacity misses. This paper presents a new algorithm for ch...
COMBINATORICS
2002
13 years 7 months ago
2002
We consider Kasteleyn and Kasteleyn-Percus matrices, which arise in enumerating matchings of planar graphs, up to matrix operations on their rows and columns. If such a matrix is ...
IEEEPACT
2009
IEEE
14 years 2 months ago
2009
IEEE
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
ICCV
2007
IEEE
14 years 9 months ago
2007
IEEE
We present a novel approach to reconstruction based superresolution that explicitly models the detector's pixel layout. Pixels in our model can vary in shape and size, and th...