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EUROMICRO
2002
IEEE
14 years 3 months ago
2002
IEEE
In this paper, we propose a new hardware unit that performs a 16 × 1 SAD operation. The hardware unit is intended to augment a general-purpose core. Further, we show that the 16 ...
EXPCS
2007
14 years 2 months ago
2007
Simulation has been the de facto standard method for performance evaluation of newly proposed ideas in computer architecture for many years. While simulation allows for theoretica...
BIOADIT
2006
Springer
14 years 1 months ago
2006
Springer
Bandwidth demands of communication networks are rising permanently. Thus, the requirements to modern routers regarding packet classification are rising accordingly. Conventional al...
ERSA
2006
13 years 11 months ago
2006
The architecture and use of caches for two-level reconfigurable hardware is studied in this paper. The considered two-level reconfigurable hardware performs ordinary reconfiguratio...
IJCAI
1997
13 years 11 months ago
1997
This paper describes an evolvable hardware (EHW) system for generalized neural network learning. We have developed an ASIC VLSI chip, which is a building block to configure a scal...