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» Time, Hardware, and Uniformity
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ICCAD
2006
IEEE
95views Hardware» more  ICCAD 2006»
14 years 7 months ago
Timing model reduction for hierarchical timing analysis
— In this paper, we propose a timing model reduction algorithm for hierarchical timing analysis based on a bicliquestar replacement technique. In hierarchical timing analysis, ea...
Shuo Zhou, Yi Zhu, Yuanfang Hu, Ronald L. Graham, ...
DDECS
2006
IEEE
146views Hardware» more  DDECS 2006»
14 years 1 months ago
Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis
Abstract-- Hard real-time systems need methods to determine upper bounds for their execution times, usually called worst-case execution times. Timing anomalies are counterintuitive...
Jochen Eisinger, Ilia Polian, Bernd Becker, Alexan...
DATE
2008
IEEE
144views Hardware» more  DATE 2008»
14 years 4 months ago
Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces
The prospective use of upcoming nanometer CMOS technology nodes (65nm, 45nm, and beyond) in bioelectronic interfaces is raising a number of important issues concerning circuit arc...
Carlotta Guiducci, Alexandre Schmid, Frank K. G&uu...
ISQED
2007
IEEE
109views Hardware» more  ISQED 2007»
14 years 4 months ago
Virtual Channels Planning for Networks-on-Chip
The virtual channel flow control (VCFC) provides an efficient implementation for on-chip networks. However, allocating the virtual channels (VCs) uniformly results in a waste of a...
Ting-Chun Huang, Ümit Y. Ogras, Radu Marcules...
ARCS
2005
Springer
14 years 3 months ago
A File System for System Programming in Ubiquitous Computing
In Ubiquitous computing small embedded sensor and computing nodes are the main enabling technologies. System programming for such small embedded systems is a challenging task invol...
Christian Decker, Michael Beigl, Albert Krohn