This paper describes a class of FPGA-specific uniform random number generators with a 2k −1 length period, which can provide k random bits per-cycle for the cost of k Lookup Ta...
Abstract. We present a hardware mechanism which dynamically detects uniform and affine vectors used in Graphics Processing Units, to minimize pressure on the register file and redu...
Modern architectural trends in instruction-level parallelism (ILP) are to increase the computational power of microprocessors significantly. As a result, the demands on memory ha...
Register files of microprocessors have often been cited as performance bottlenecks and significant consumers of energy. The robust and modular nature of quasi-delay insensitive (Q...